Clock pulse generator for multi-phase signaling

ABSTRACT

A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.61/954,483, filed Mar. 17, 2014, the contents of which are incorporatedby reference herein in their entirety.

TECHNICAL FIELD

This application relates to clock generation, and more particularly to aclock generator for multi-phase signaling.

BACKGROUND

Transmission of multi-bit words typically occurs over multi-wire buses.For example, an eight-bit word may be transmitted over a bus havingeight wires, one for each bit. But in such conventional busses, each bitcarried on a given wire is independent of the remaining bits. As thedata rates increase, such conventional communication becomes problematicin that the various bits in a word become skewed from each other as theword propagates over the bus.

Given the issues with skew between multiple bits in high-speedcommunication, various serializer/deserializer (SERDES) systems havebeen developed. A SERDES transmitter serializes a multi-bit word into aseries of corresponding bits for transmission to a receiver. There canthen be no such skew between adjacent bits on a multi-wire bus since asingle transmission line (which may be differential) is used in a SERDESsystem. The SERDES receiver deserializes the received serial bit streaminto the original word. However, the SERDES transmission line and thereceiver load introduce distortion as the data transmission rateexceeds, for example, 10 GHz. Adjacent bits in the serial bit streamthen begin to interfere with each other. Complicated equalizing schemesbecome necessary to fight the resulting inter-symbol interference andthus it becomes difficult to push SERDES data transmission rates everhigher.

To increase data transmission rates over the SERDES limitations, athree-phase signaling protocol has been developed in which threetransmitters drive three separate transmission lines. The followingdiscussion will be directed to the clock generation upon receipt ofsignals from current-mode transmitters that either source or receivecurrent but voltage-mode transmission may also be used. Since the netcurrent must be zero, all three transmitters cannot be active (eithertransmitting or receiving current) in a three transmitter system.Similarly, there must be current injected and received so all threetransmitters cannot be inactive for any given symbol. So that means thattwo of the three transmitters will be active for each symbol, with onesourcing current and the other receiving current. From a set of threetransmitters, there are three distinct pairs of transmitters that can beactive. Within each pair, there are two possibilities depending uponwhich transmitter is sourcing versus which transmitter is receiving.There are thus six distinct combinations of two active transmitters eachsourcing or receiving a given amount of current in a three-transmittermulti-phase system. Each distinct combination of active transmitters maybe denoted as a symbol. Since there are six possible symbols, eachtransmitted symbol represents 2.5 bits. In this fashion, datatransmission speeds may be more than doubled over binary transmission atthe same symbol rate using a single channel, albeit at the cost ofincreased power consumption.

In the receiver for a multi-phase communication system, a frontendcircuit decodes the received differential currents to produce thecorresponding binary symbol. The six different symbols may berepresented by six binary words: [100], [010], [001], [110], [101], and[011]. The bits in these symbols may be represented by the binaryvariables A, B, and C. For example, the symbol [100] corresponds to A=1,B=0, and C=0. To ensure that one of the three binary variables changesstate for every transmitted symbol, no self-transition is allowed. Forexample, suppose the symbol [001] had just been received. The subsequentsymbol cannot be [001] as this would violate the ban againstself-transition. In this fashion, a clock can be extracted from everyreceived symbol from the guaranteed binary transition of at least one ofthe binary signals. In practice, however, the extraction of the clockmay be complicated by skew between the binary signals that are generatedin the receiver frontend circuit responsive to the differential currentson the transmission lines from the transmitter. To generate the clock,each signal A, B, and C may then drive its own pulse generator as shownin FIG. 1A. The frontend circuit that decodes the differential currenttransmission to produce the binary data signals A, B, and C is not shownfor illustration clarity. An A pulse generator receives the A datasignal, a B pulse generator receives the B data signal, and a C pulsegenerator receives the C data signal. Each pulse generator generates apulse responsive to each rising and falling edge (binary shift orchange) in the corresponding data signal.

An OR gate ORs the generated pulses from the pulse generators to producethe clock signal. FIG. 1B illustrates the resulting signal waveforms forideal behavior (zero skew between the data signals). The pulsegenerators are configured to generate a pulse at a fifty percent dutycycle with regard to the data word period such that the resulting clocksignal has a 50% duty cycle as well. Since there is a guaranteed binarytransition of at least one of the A, B, and C signals every data wordperiod, at least one of the pulse generators will generate a pulseaccordingly. For example, both signals A and B have a binary transitionat the beginning of a data word period B0. Thus, pulse generator A andpulse generator B both generate a pulse in period B0. Similarly, signalsA and C both have a binary transition at the beginning of a subsequentdata word period B1 so that the pulse generators A and C pulseaccordingly. In another data word period B2, only signal B has a binarytransition but only one such transition is necessary for the clocksignal to continue cycling. The clock (Bit Clk) generated from the ORingof the pulse generator output signals has the desired cycling in eachbit period.

But as signal transmission speeds are increased, it becomes more andmore difficult to have the zero skew between signals A, B, and C shownin FIG. 1B. FIG. 1C illustrates the more generic case in which signalsA, B, and C become jittered and skewed as they propagate through thereceiver at high data rates. For example, in a data word period B0, datasignal A transitions synchronously with the beginning of the data wordperiod. But data signal B is skewed with regard to the period boundarysuch that its transition occurs later. As a result, the ORing of theresulting pulses produces a duty cycle of substantially greater than 50%in period B0. Similar distortion and jiitter occurs for the remainingsymbol periods as well. The resulting duty cycle distortion and jitterfor such a recovered clock produces bit errors when the clock is used tosample the data signals.

Accordingly, there is a need in the art for improved clock generationcircuits and techniques for data transmission systems using multi-phaseencoding.

SUMMARY

A clock generator is provided for a multi-phase receiver. As usedherein, the term “multi-phase” refers to signaling over multipletransmission lines in which the signaling on each transmission linedepends upon the signaling over the remaining transmission lines. Forexample, in a three-phase system, three transmitters drive threetransmission lines with either current-mode or voltage-mode signals. Thefollowing discussion will assume without loss of generality thattransmitters are current-mode transmitters since the concepts andtechniques disclosed herein are readily adapted for voltage-modesystems. Each current-mode transmitter either sources current, sinkscurrent, or is inactive. Since the net current must be zero, only two ofthe three transmitters can be active in sourcing or sinking current forany given symbol transmission. The clock generator discussed hereinprocesses the bit signals from the receiver's frontend circuit. Forexample, in a three-phase current-mode system, the receiver's frontendcircuit determines the current flow direction on the two active lines togenerate a three-bit data word having bits that may be designated as A,B, and C. Such frontend circuits are conventional in multi-phasereceivers. As data transmission rates are pushed ever higher, these bitsbecome skewed with respect to each other. But the non-overlapping clockgeneration techniques disclosed herein accommodate this skew without anyresulting duty cycle distortion in the clock signal generated from theskew in the data words.

In a three-phase current-mode system in which the sourced or receivedcurrents are all equal, the three transmission lines cannot all beactive at the same time because then there would not be a net zerotransmitted current. So the data word [111] is not allowed. Similarly,the three transmission lines cannot all be inactive as then there wouldbe no transmitted currents. So the data word [000] is also not allowed.There are thus six allowed data words: [001], [010], [100], [110],[101], and [011]. Note that these data words are generated by thereceiver frontend circuit after decoding the currents or voltages on themultiple transmission lines. In other words, the data word [001] inwhich the A and B data bits are each zero and the C data bit equals 1does not correspond to just one transmission line being active sincethere must be two active transmitters where one is sourcing current andthe other is sinking current. Thus, the data words are bits generated bythe receiver's frontend circuit upon decoding the signals received onthe transmission lines. Further details regarding the decoding of datawords in a multi-phase receiver are discussed in commonly-assigned U.S.application Ser. No. 12/042,362, filed Mar. 5, 2008, the contents ofwhich are incorporated herein in their entirety.

The clock generator includes a pull-down signal generator that processespairs of bits within each data word to assert one of a plurality ofpull-down signals. The pull-down signals correspond on a one-to-onebasis with the data words. For example, since there are six possibledata words in a three-phase system, there would then be sixcorresponding pull-down signals. The pull-down signal generator isconfigured so as to assert the pull-down signal that uniquelycorresponds to a current data word.

The clock generator also includes a plurality of pull-down circuitscorresponding to the plurality of pull-down signals. Each pull-downcircuit responds to the assertion of the corresponding pull-down signalto discharge a common node coupled to all the pull-down circuits. Theclock generator further includes a pull-up circuit that functions torecharge the discharged common node back to a power supply voltage. Theclock generator generates the clock from this discharging and chargingof the common node. In the presence of skew between the bits in a givenone of the data words, the pull-down signal generator may assert morethan one pull-down signal instead of just asserting the pull-down signalcorresponding to the given data word. But this skew does not affect thegenerated clock because of the relative delays within the pull-downcircuits and the pull-up circuit as discussed further herein. These andother advantageous features may be better appreciated through thefollowing detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram for a conventional multi-phase receiver's clockgeneration circuit.

FIG. 1B is a timing diagram for the data signal transitions and theresulting generated pulses and clock for the clock generator of FIG. 1Awhen the data signals are not skewed.

FIG. 1C is a timing diagram for the data signal transitions, generatedpulses, and clock for the clock generator of FIG. 1A when the datasignals are skewed with respect to each other.

FIG. 2A is a diagram of logic circuits to process the data signals froma multi-phase receiver into corresponding pull-down signals inaccordance with an embodiment of the disclosure.

FIG. 2B is diagram of a clock generation circuit that uses the pull-downsignals from FIG. 2A to generate a single rate clock in accordance withan embodiment of the disclosure.

FIG. 2C is a circuit diagram of a pull-down circuit for the clockgeneration circuit of FIG. 2B.

FIG. 3A is a timing diagram for the common node voltage in the clockgeneration circuit of FIG. 2B.

FIG. 3B is a timing diagram for the clock signal generated from thecommon node voltage of FIG. 3A.

FIG. 4 is a diagram of a clock generation circuit that uses thepull-down signals of FIG. 2A to generate two half rate clocks inaccordance with an embodiment of the disclosure.

FIG. 5 is a flowchart for a method of use of a clock generation circuitin accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

A non-overlapping clock generator for multi-phase receivers is provided.As used herein, a “multi-phase receiver” denotes a receiver of signalstransmitted on a plurality of transmission lines such that any givensignal is not independent of the signals on the remaining transmissionlines. In contrast, consider conventional signaling on a multi-bitbus—the value of a given bit in a digital word carried on the bus isindependent of whether the remaining bits are ones or zeroes. But thatis not the case for a multi-phase system. For example, the receiver in acurrent-mode three-phase system determines the current direction(sourced or received) for the two active lines. The identity of theactive transmission line and their current directions forms a receivedsymbol that the receiver frontend circuit decodes into three-bit datawords.

The three bits in the data words may be represented by threecorresponding variables A, B, C. For example, if the received symbol onthe three transmission lines is decoded into the data word [100], then Band C are both zero whereas A is one. As discussed with regards to FIG.1C, the bits in the data words become skewed with respect to each otherat high data transmission rates. Such skew becomes problematic if eachbit signal A through C drives its own pulse generator circuit thatpulses upon sensing a binary transition of the corresponding bit signal.For example, both signals A and B change binary states from an initialdata word [100] to a successive data word [010]. If each signal A and Bthen drives its own pulse generator circuit as discussed with regard toFIG. 1A, then both pulse generators circuits will pulse from the binarytransitions in the corresponding A and B signals. Such plural pulsegeneration within a single data word period is denoted herein as“overlapping” pulse generation. Such overlapping pulse generation isinnocuous if there is no skew between the A, B, and C signals asdiscussed with regard to FIG. 1B. But there is inevitable skew such asshown in FIG. 1C as the data transmission rates are increased. Theoverlapping pulses then produce a clock pulse that has a distorted dutycycle. The advantageous clock generation circuit disclosed hereinobviates this skew through processing of the data words such that aconstant clock duty cycle is achieved despite overlapping pulsegeneration.

There is no overlapping pulse generation if there is no skew between thebits in the data words. This processing of non-skewed data words will bediscussed with regard to a current-mode three-wire system. However, itwill be appreciated that the non-overlapping principles disclosed hereinmay be broadly applied to voltage-mode systems and to multi-phasereceivers processing more than three transmission lines. Theadvantageous processing of the allowed data words [100], [010], [001]will first be discussed. Since there are three bits A, B, and C in eachof these words, there are only three distinct pairs of bits that may beformed: A and B, B and C, and A and C. Since each of the preceding datawords has just one positive bit, each of these data words has a uniquepair of zero bits. For example, in data word [100], B and C are bothzero. These bits B and C are not both zero in the other remaining datawords. Similarly, in data word [010], bits A and C are both zero but arenot both zero in the other remaining data words. The pull-down signalgenerator for the three pairs of bits may thus comprise a correspondingNOR gate for each bit pair to produce pull-down signals that will beused to generate non-overlapping pulses. In particular, each NOR gateprocesses its own corresponding bit pair to generate a correspondingpull-down signal that is received by a corresponding pull-down circuitcoupled to a common node. Should a NOR gate assert its pull-down signal,the corresponding pull-down circuit discharges the common node for afirst pulse duration.

The pull-down signal generator must also accommodate the processing ofthe remaining three data words [110], [101], and [011]. Each of theseremaining data words has a unique pair of two positive bits. Forexample, bits A and B are both 1 in the data word [110] while these sametwo bits are not both equal to one for any of the remaining data words.Similarly, the bit pair of B and C are both equal to one in the dataword [011] but are not both ones in any of the remaining data words. Thepull-down signal generator may thus comprise three AND gates in additionto the three NOR gates just described. Each unique bit pair AB, BC, andAC (note that the order doesn't matter within the bit pairs) drives itsown corresponding AND gate that in turn drives a corresponding pull-downcircuit coupled to the common node. There are thus six pull-downcircuits in a three-wire embodiment: three for the three NOR gates andthree for the three AND gates. Three pull-down circuits are driven bycorresponding NOR gates that NOR their unique pair of the bits in thecurrent data word. Three remaining pull-down circuits are each driven bycorresponding AND gates that AND their unique pair of the bits in thecurrent data word. Each pull-down circuit will pulse the common node lowfor a first delay period (denoted herein as D1).

Note the difference with regard to the clock generation discussed withregard to FIG. 1B in which a non-skewed data word triggered overlappingpulse generation. In contrast, the clock generator disclosed herein willpulse only once for each non-skewed data word. There is no overlappingpulsing of the common node if there is no skew in the correspondingdigital word. However, such non-skewed digital words become difficult toachieve as the data rates are increased. The clock generation circuitdisclosed herein may trigger overlapping discharges of the common nodeanalogous to the overlapping pulses discussed with regard to FIG. 1C inresponse to skew in the data words. But the resulting overlapping pulsesdo not introduce duty cycle distortion for the disclosed clock generatorso long as the following delay conditions are satisfied. In particular,the skew between the bits in each data word is innocuous so long as theskew does not exceed the first delay period D1. Given such a condition,the maximum length for an overlapping pulse by the triggered pull-downcircuits is a sum (D1+TS), where TS is the skew time in thecorresponding data word. In that regard, the overlapping pulsing low ofthe common node may be deemed to being at an initial time. The clockgenerator includes a pull-up circuit that recharges the common nodeafter the expiration of a second delay period (designated herein as D2)from the initial time. This second delay period is controlled so that D2is at least twice that of D1. Since D1 is greater than or equal to TS,D2 is thus greater than or equal to the sum of (D1+TS). The pull-up ofthe common node voltage will thus occur after expiration of the pull-updelay D2 from the start of the delay period D1. Note that TS can varyfrom data word to data word but the common node will be discharged forthe same amount of time—namely, for D2. In other words, so long as theskew time TS is maintained to be less than D1, it has no effect on thepull-down time for the common node. Since the clock generation circuitgenerates the clock responsive to the discharging and charging of thecommon node, the skew time TS thus has no effect on the clock dutycycle. These advantageous features may be better appreciated with regardto the following example embodiments.

An example pull-down signal generation circuit 250 for processingsignals A, B, and C is shown in FIG. 2A. An AND gate 255 processes the Aand B bits to produce the product AB. The same pair of bits drives a NORgate 270 to produce the complement sum (A nor B). Similarly, an AND gate260 processes the B and C bits to produce the product BC whereas a NORgate 275 processes this pair of bits to produce the complement sum (Bnor C). Finally, an AND gate 265 processes the A and C bits to producethe product AC whereas a NOR gate 280 processes the same bits into thecomplement sum (A nor C). Each resulting product and complement sumsignal functions as a unique pull-down signal that may trigger apull-down of a common node.

A clock generation circuit 200 shown in FIG. 2B includes a pull-downcircuit for each pull-down signal. For example, there is a pull-downcircuit 206 that receives the product AB. The product AB is thus thepull-down signal that triggers pull-down circuit 206. Similarly, apull-down circuit 207 receives the complement sum (A nor B), and so on.Each pull-down circuit functions to discharge a common (Comm) node for afirst delay period D1 responsive to its pull-down signal being asserted(equaling binary one in an active high system).

Each pull-down circuit may be identical but for which pull-down signalit processes. Pull-down circuit 206 is shown in more detail in FIG. 2C.Two NMOS transistors M1 and M2 are arranged in series between ground andthe Comm node. The pull-down signal (in this case, the AB product)drives the gate of the M1 transistor. The M1 transistor is thus offwhile the AB product is not asserted. The pull-down signal is invertedand delayed through an inverter to produce a delayed complement ABproduct (ABd) that drives the gate of the M2 transistor such that the M2transistor is switched on while the AB product is not asserted. Upon theassertion of the AB product, the M1 transistor switches on but the M2transistor also stays on due to the delay in the de-assertion of the ABdsignal—it is this delay that equals D1. The Comm node will thendischarge to ground through the switched on pair of transistors M1 andM2. The signal ABd will not switch low in response to the activation ofthe pull-down signal AB until after expiration of the delay period D1whereupon the M2 transistor switches off to stop the discharge of theComm node. The pull-down signal AB will eventually be de-asserted uponthe receipt of the next data word since self-transitions (repetition ofthe same data word) are not allowed. In this case, the assertion of thepull-down signal AB corresponds to the receipt of the [110] data word.That data word will not be received as the subsequent data word due tothe prohibition against self-transition. Thus, the subsequent data wordwill not be [110] such that the AB pull-down signal is then de-assertedaccordingly. In one embodiment, the array of pull-down circuits may bedeemed to comprise a means for discharging a common node for a firstdelay period responsive to each pull-down signal.

The skew between bits in a current data word being processed by clockgeneration circuit 200 causes overlapping discharge of the Comm node.For example, suppose that the previous data word was [001] and thecurrent data word is [110]. Bits A and B were thus both zero in theprevious data word and should change simultaneously to logical ones atthe beginning of the current data word. But suppose further that bit Bis skewed by the skew time TS with regard to the transition of bit A.The beginning of the current data word would thus actually present as[100] and not change to the proper value of [110] until after the skewtime TS has elapsed. The NOR of bits B and C will thus trigger theinitial discharge of the Comm node. This discharge would last the delayperiod D1 except that it is followed by the “correct” discharge of theComm node as triggered by the AND of bits A and B at time T2 for anotherdelay period D1. The overlapping discharge by the two resultingpull-down signals discharges the Comm node for a period (D1+TS). TheComm node then floats until it is recharged by the pull-up circuit afterthe delay period D2 has expired from the initial discharge of the Commnode. The skew time TS may vary from data word to data word but has noeffect since the pull-up of the Comm node is triggered after the delaytime D2, which is greater than or equal to twice the delay period D1 andthus is greater than the sum (D1+TS).

The Comm node voltage may be buffered through a first set of buffers 220to output the clock signal. In one embodiment, the first set of buffers220 may be deemed to comprise a means for generating a clock responsiveto the charging and discharging of the common node. Buffers 220 may alsocomprise inverters. The resulting clock pulse may then be used to alignthe bits in the data words before processing in a de-serializer (notillustrated). The clock pulse also feeds back through another set ofbuffers 220 to drive the gate of a PMOS transistor 205 as a bias PMOS(biasp) signal. Buffers 220 and PMOS transistor 205 comprise a pull-upcircuit for recharging the Comm node voltage back to a power supplyvoltage VDD. In one embodiment, buffers 220 and PMOS transistor 205 maybe deemed to comprise a means for charging the common node to a powersupply voltage after a second delay period from the discharge of thecommon node. The biasp signal is of the same polarity as the voltage ofthe Comm node and will thus be pulsed low in response to the Comm nodevoltage after a loop delay D2 resulting from the propagation of the Commnode voltage through buffers 220. PMOS transistor 205 will thus switchon when the biasp signal is discharged. PMOS transistor 205 has itssource tied to a power supply node providing a power supply voltage VDD.The drain of PMOS transistor 205 couples to the Comm node so that theComm node voltage is raised to VDD in response to the discharge of thebiasp signal. The assertion of the Comm node voltage then propagatesthrough buffers 220 according to the loop delay D2 to switch off PMOStransistor 205 from the assertion of the biasp signal.

In alternative embodiments, the delay time D2 may be configured so as tobe just greater than or equal to D1 as opposed to being twice D1. Insuch embodiments, the pull-up of the Comm node voltage may overlap withthe pull-down of Comm node voltage. Thus, in embodiments in which thedelay period D2 is not greater than or equal to twice D1, PMOStransistor 205 may be made relatively large as compared to NMOStransistors M1 and M2.

To keep the Comm node from floating when the PMOS transistor 205 is off,the biasp signal is inverted through an inverter 215 to drive the gateof a weak keeper PMOS transistor 210. The source of the weak keeper PMOStransistor 215 couples to the power supply node VDD and its draincouples to the Comm node. The weak keeper PMOS transistor 210 thusfunctions to weakly charge the Comm node voltage to VDD when the PMOStransistor 205 is off. The NMOS transistors M1 and M2 in each pull-downcircuit are relatively strong compared to weak PMOS transistor 210 andthus can discharge the Comm node voltage despite the weak keeper PMOStransistor 210 being switched on.

Some example timing for the Comm node voltage is shown in FIG. 3A for aninitial data word U1 ₀ followed by a subsequent data word U1 ₁. Theresulting clock signal voltage is shown in FIG. 3B. Each data word has abit period U1. With regard to the beginning of each data word, the Commnode voltage is discharged for the period D2 as discussed previously. Inreality, the Comm node voltage does not float as shown subsequent to theexpiration of the pull-down time (D1+TS) but instead would be weaklycharged by weak keeper transistor 210. But note that the inverters thatconstitute buffers 220 have a threshold voltage of approximately VDD/2with regard to their inversion. So long as the weak pull-up of the Commnode does not rise above this threshold voltage, it may be ignored withregard to the release of the pull-down on the Comm node voltage by thecorresponding pull-down circuits until the Comm node voltage is stronglycharged back to VDD after the expiration of the D2 delay period.Accordingly, the weak pull-up by weak keeper transistor 210 is not shownin FIG. 3A in that it has no effect on the resulting clock signalgeneration. In addition, note that the clock signal does not respond tothe discharge of the Comm node voltage until whatever delay is requiredto propagate this voltage change through the first set of buffers 220has expired. This delay is not shown in FIG. 3B for illustrationclarity.

As shown in FIG. 3A, the skew time TS may vary widely from data word todata word but so long the sum of (D1+TS) is less than D2, this varyingskew has no effect on the resulting clock generation. One can readilyappreciate that the bit period U1 may be greater than or equal to twiceD2 because it takes two loop delays D2 for the PMOS transistor 205 to beswitched off in anticipation for the subsequent data word. If the bitperiod were less than twice D2, PMOS transistor 205 would not be resetprior to the arrival of the subsequent data word. In alternativeembodiments, the bit period U1 may be less than twice the delay periodD2.

Designing buffers 220 so that the bit period U1 equals at least twicethe delay period D2 may become problematic as the data transmissionspeeds are increased. As the data rates are increased, the delay periodinterval U2 (and thus the delay period D1) must shrink accordingly. Butthe receiver may be located in, for example, a DRAM integrated circuitthat uses a relatively slow semiconductor process. In contrast, thetransmitter may be located in, for example, a system-on-a-chip (SOC)that uses a much faster CMOS semiconductor process. The receiver maythus be unable to generate a delay period D2 that is one half or lessthan the data interval. To satisfy the required timing, two half-rateclocks may be generated. An example half-rate clock generator 400 for apair of half-rate clocks CLKY and CLKX is shown in FIG. 4. A firstpull-down circuit 405 represents the six pull-down circuits discussedwith regard to clock generator 200. Similarly, these six pull-downcircuits are duplicated in a second pull-down circuit 406. Eachpull-down circuit couples to a corresponding Comm node. However, thiscoupling is through a switch NMOS transistor rather than a directcoupling as discussed with regard to clock generator 200. In thatregard, pull-down circuit 405 couples to a CommY node through a switchNMOS transistor M3. Similarly, pull-down circuit 406 couples to a CommXnode through a switch NMOS transistor M4.

Switch transistors M3 and M4 are switched in a complementary fashionthrough a pair of PMOS transistors P1 and P2. The CommY node couplesthrough a buffer to the gate of P1 transistor, which has its sourcecoupled to a power supply node providing the power supply voltage VDDand its drain coupled to the gate of the switch transistor M4. If theCommY node is pulsed low through its pull-down circuit 405, the P1transistor will thus charge the gate of the switch transistor M4 toensure that pull-down circuit 406 can discharge the CommX node when thenext data word is received. At the same time, an inverter 420 invertsthe low voltage of the CommY node to switch on an NMOS transistor M5.The source of transistor M5 couples to ground whereas its drain couplesto the drain of the transistor P2 and also to a node 425 that couples tothe gate of switch transistor M3. The switching on of transistor M5 thusgrounds node 425 to switch off switch transistor M3. An inverter 430inverts the voltage of node 425 to drive a clock Y (CLKY) signal high inresponse to the pulsing low of the CommY node.

The pulsing low of the CommY node then propagates through the delay 2loop delay provided by buffers 220 to pull a biaspY signal low thatdrives the gate of a PMOS transistor 410. Transistor 410 is analogous toPMOS transistor 205 discussed previously in that transistor 410 has itssource tied to the power supply node and a drain coupled to the CommYnode. The pulsing low of the CommY node is thus ended after theexpiration of the loop delay D2 by transistor 410, which then conductsto charge the CommY node back to VDD. This charging of the CommY nodethen switches off transistor M5 to stop the discharge of node 425. Thus,node 425 will go high after transistor M5 goes off to pull the CLKYsignal low. A weak keeper device KY such as a PMOS transistor functionsto weakly charge node 425 to VDD.

Another weak pull-up device KY functions to weakly charge a node 435 toVDD. Node 435 couples to the gate of switch transistor M4. At thereceipt of the next data word, pull-down device 406 can thus dischargethe CommX node because switch transistor M4 will be on. The pulsing lowof the CommX node voltage is inverted through an inverter 440 that thendrives the gate of a transistor M6 to switch transistor M6 on. Thesource of transistor M6 couples to ground whereas its drain couples tonode 435 and to the drain of transistor P1. Transistor P1 is off at thistime so the switching on of transistor M6 grounds node 435. An inverter445 inverts the voltage for node 435 to drive a clock X (CLKX) signalhigh. The pulsing high of the CLKX signal is brought low after theexpiration of a loop delay through buffers 220 to pull a biaspX signallow to switch on a PMOS transistor 415. Transistor 415 has its sourcetied to the power supply node and a drain coupled to node 425. Theswitching on of transistor 415 then charges the CommX node to VDD, whichswitches off transistor M6. Node 435 is then weakly charged back to VDDso that the CLKX signal is pulsed low.

Whenever one of the clock signals CLKX or CLKY goes high, note that theremaining clock signal is driven low by the feedback through the P1 orP2 transistors. For example, if the CLKX signal is high because theCommX node has been pulsed low, then the transistor P2 is switched oncharge node 425 high. The high voltage for node 425 is then invertedthrough inverter 430 to drive the CLKY signal low. Similarly, if theCKLY clock signal is pulsed high, then the CommY node is low, whichswitches on transistor P1 to pulls node 435 high. This high voltage isinverted through inverter 445 to drive the CLKX signal low.

Referring again to the loop delay D2 through buffers 220 whenever one ofthe Comm X or CommY nodes is pulsed low, note that it need not be ½ orless than the unit interval for each data word. In contrast, signalgenerator 200 required such a relationship between the loop delay D2 andthe unit interval. But the half-rate clock generator 400 may relax thisrequirement because the clocks reset each as just discussed. Forexample, the CommX node need not be recharged to VDD before thesubsequent data word is received since the subsequent data word will beused to discharge the CommY node instead. Thus, buffers 220 may berelatively slow such that the loop delay D2 need merely be less than orequal to the unit interval.

Half-rate clock generator 400 may be generalized in alternativeembodiment to generate other fractional clock rates. Referring back tothe feedback through the P1 and P2 transistors, this pulsing of thenodes 425 and 435 may be thought of as passing of a token in a tokenring. If one of the nodes is pulsed low, the next node in the token ringis pulsed high. This subsequent node in the token ring would then bedischarged upon receipt of the next data word, whereupon the token ispassed to the subsequent stage to the subsequent stage, and so on. Forexample, if there are three such stages, each stage could generate a ⅓rate clock.

A method of generating a clock will now be discussed with regard to theflowchart shown in FIG. 5. A step 500 comprises processing pairs of bitsfor a skewed digital word to assert a first pull-down signal at aninitial time responsive to a binary change of an initial-arriving bit ina skewed digital word and to assert a second pull-down signal at asubsequent time responsive to a binary change of a subsequent-arrivingbit in the skewed digital word, the subsequent time being delayed withregard to the initial time by a skew time for the skewed digital word.An example of the first pull-down signal is discussed above with regardto the receipt of a data word that is supposed to be received as [110]but because of skew is initially received as [100]. NORing bits B and Cwould initially trigger a first pull-down signal when bit C transitionslow that would be followed by the ANDing of bits A and B when bit Bfinally transitions high to trigger a second pull-down signal.

The method also includes an act 505 that is responsive the assertion ofthe first pull-down signal and comprises discharging a node for a firstdelay period after the initial time. The discharge of the Comm nodevoltage at the beginning of data word U1 ₀ for a period D1 discussedwith regard to FIG. 3A is an example of act 505.

The method also includes an act 510 that is responsive to the assertionof the second pull-down signal and comprises extending the discharge ofthe node past the first delay period by the skew time. This skew time isdenoted as TS as discussed with regard to FIG. 3A is an example of act510.

The method also includes an act 515 of charging the node to a powersupply voltage after a second delay period has expired from thedischarge of the node at the initial time. The charging of the Comm nodevoltage to VDD after expiration of the D2 delay period as discussedabove with regard to FIG. 3A is an example of act 515.

Finally, the method includes an act 520 of generating a clock signalfrom the charging and discharging of the node. The generation of theclock in the clock generator 200 of FIG. 2B is an example of act 520.

It will thus be appreciated that many modifications, substitutions andvariations can be made in and to the materials, apparatus,configurations and methods of use of the devices of the presentdisclosure without departing from the spirit and scope thereof. In lightof this, the scope of the present disclosure should not be limited tothat of the particular embodiments illustrated and described herein, asthey are merely by way of some examples thereof, but rather, should befully commensurate with that of the claims appended hereafter and theirfunctional equivalents.

We claim:
 1. A circuit, comprising: a pull-down signal generatorconfigured to generate a plurality of pull-down signals corresponding toa plurality of digital words; a plurality of pull-down circuitscorresponding to the plurality of pull-down signals, each pull-downcircuit configured to discharge a common node for a first delayresponsive to an assertion of the corresponding pull-down signal by thepull-down signal generator; a pull-up circuit configured to bias thecommon node to a power supply voltage after a second delay from thedischarge of the common node.
 2. The circuit of claim 1, wherein thepull-down signal generator comprises a plurality of logic gatesconfigured to process pairs of bits from received ones of the digitalwords.
 3. The circuit of claim 2, wherein the plurality of logic gatescomprise a first plurality of AND gates and a second plurality of NORgates.
 4. The circuit of claim 1, wherein each pull-down circuitcomprises a pair of NMOS transistors coupled in series between groundand the common node.
 5. The circuit of claim 4, wherein a first one ofthe NMOS transistors in each pull-down circuit has a gate coupled to thecorresponding pull-down signal and a drain coupled to the common node.6. The circuit of claim 5, wherein each pull-down circuit furthercomprises an inverter configured to invert the corresponding pull-downsignal into a delayed pull-down signal, and wherein a second one of theNMOS transistors in each pull-down circuit has a gate driven by thedelayed pull-down signal and a source coupled to ground.
 7. The circuitof claim 6, wherein each pull-down circuit's inverter further comprisesa buffer configured to delay the delayed pull-down signal such that thefirst delay period is greater than or equal to an expected skew betweenbits in the digital words.
 8. The circuit of claim 7, wherein thepull-up circuit comprises a PMOS transistor coupled between a powersupply node and the common node, and wherein the pull-up circuit furthercomprises at least one buffer coupled to the common node, the at leastone buffer being configured to discharge a delayed signal upon theexpiration of the second delay period after the discharge of the commonnode.
 9. The circuit of claim 8, wherein the at least one buffercomprises a plurality of buffers configured so that the second delayperiod is greater than or equal to twice the first delay period.
 10. Thecircuit of claim 1, wherein the circuit is located within a receiverthat is configured to use a clock signal derived from the discharge andbias of the common node responsive to each digital word.
 11. The circuitof claim 10, wherein the receiver is part of an integrated circuit for adynamic random access memory (DRAM).
 12. The circuit of claim 8, furthercomprising a weak keeper device configured to weakly charge the commonnode to the power supply voltage responsive to the discharge of thedelayed signal.
 13. The circuit of claim 12, wherein the weak keeperdevice comprises a PMOS transistor.
 14. The circuit of claim 13, furthercomprising an inverter configured to invert the delayed signal into aninverted signal that drives a gate of the PMOS transistor.
 15. A method,comprising: processing pairs of bits for a skewed digital word to asserta first pull-down signal at an initial time responsive to a binarychange of an initial-arriving bit in a skewed digital word and to asserta second pull-down signal at a subsequent time responsive to a binarychange of a subsequent-arriving bit in the skewed digital word, thesubsequent time being delayed with regard to the initial time by a skewtime for the skewed digital word; responsive to the assertion of thefirst pull-down signal, discharging a node for a first delay periodafter the initial time; responsive to the assertion of the secondpull-down signal, extending the discharge of the node past the firstdelay period by the skew time; charging the node to a power supplyvoltage after a second delay period has expired from the discharge ofthe node at the initial time; and generating a clock signal from thedischarging and charging of the node.
 16. The method of claim 15,wherein the skewed digital word is a three-bit digital word having bitsA, B, and C, and wherein processing pairs of bits for each receiveddigital word comprises processing a pair of the A and B bits, a pair ofthe B and C bits, and a pair of the A and C bits.
 17. The method ofclaim 15, wherein processing each pair of bits comprises forming aproduct of the pair of bits and forming a complement sum of the pair ofbits.
 18. The method of claim 15, wherein discharging the node for thefirst delay period comprises turning on a first transistor responsive tothe assertion of the selected pull-down signal to couple the node toground though a second transistor.
 19. The method of claim 18, whereindischarging the node for the first delay period further comprisesinverting and delaying the asserted pull-down signal by the first delayperiod to produce a delayed pull-down signal that switches off thesecond transistor to prevent further discharge of the node.
 20. Themethod of claim 15, wherein charging the node to the power supplyvoltage comprises buffering a voltage for the node through at least onebuffer to create a delayed discharged signal that switches on a switchafter the expiration of the second delay period to couple the node to apower supply node supplying the power supply voltage.
 21. A circuit,comprising: a pull-down signal generator configured to generate aplurality of pull-down signals corresponding to a plurality of digitalwords, the pull-down signal generator being further configured to assertthe pull-down signal corresponding to a received one of the digitalwords; means for discharging a common node for a first delay periodresponsive to each asserted pull-down signal; means for charging thecommon node to a power supply voltage after a second delay period fromthe discharge of the common node; and means for generating a clockresponsive to the charging and discharging of the common node.
 22. Thecircuit of claim 21, wherein the means for generating a clock comprisesa means for generating a fractional-rate clock.
 23. The circuit of claim21, wherein the means for generating a clock comprises a means forgenerating a half-rate clock.